The present invention relates to a semiconductor device that functions as a DTMOS or a MISFET having a heterojunction active region.
In recent years, portable information terminal units driven by a battery are widely used. In such units, there is a strong demand for reducing the power supply voltage without compromising high speed operations in order to prolong the battery lifetime. Reducing the threshold voltage is effective in realizing high speed operations. In this case, however, the leakage current at the time when the gate is off becomes large, so that it is inevitable that there should be a lower limit for threshold voltage.
As a device that can solve this problem and has a small leakage current at a low voltage and high driving ability, a device called DTMOS (Dynamic Threshold Voltage MOSFET) has been proposed, as disclosed in, for example, a literature xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d, by F. Assaderaghi et. al., IEDM94 Ext. Abst. P.809.
FIGS. 1 and 2 are a cross-sectional view and a plan view schematically showing a conventional DTMOS structure, respectively. As shown in FIG. 1, the conventional DTMOS uses a SOI substrate including a p-type silicon substrate (pxe2x88x92 Si Sub), a buried oxide film layer (Buried Oxide) and a semiconductor layer, which serves as a substrate active region. The conventional DTMOS further includes a gate insulator film (SiO2) on the substrate active region, a gate (n+ poly-Si), source and drain regions (n+ layer) in regions on both sides of the gate of the substrate active region, a channel region (a surface portion of the p layer) in a region between the source and drain regions of the substrate active region. A substrate region below and on the sides of the channel region (body) is connected to the gate electrode by wiring for electrical short-circuit. When a bias voltage Vg is applied to the gate while the gate is tied to the body, a forward bias voltage having the same magnitude as that of the gate bias voltage Vg is applied to the channel region via the body. Thus, this DTMOS has the same state as that of a regular MOS transistor at the time when the gate bias is off, and the body is biased in the forward direction as the gate bias voltage Vg is increased at the time when the gate bias is on (this occurs because the energy level of the conduction band edge of the channel region is decreased in the n-channel type MOS transistor shown in FIG. 1. Therefore, the threshold voltage Vt drops.
When such a DTMOS is compared with a regular MOS transistor (transistor where the gate and the body are not short-circuited) formed on a SOI substrate, the leakage current of the DTMOS is equal to that of the regular transistor at the time when the gate bias is off. On the other hand, since the threshold voltage drops at the time when the gate bias is on, as described above, the gate over drive effect increases, so that the driving ability increases significantly. Furthermore, in the DTMOS, there is substantially no electric potential difference between the gate and the channel region, and therefore the electric field in the vertical direction on the surface of the substrate is significantly small, compared with that of the regular transistor. As a result, the degradation of the mobility of carriers due to an increase of the electric filed in the vertical direction is suppressed, so that the driving ability is increased significantly.
Thus, the DTMOS functions as a transistor that can operate at high speed at a low threshold voltage, i.e., a low power supply voltage, as long as the operating voltage is in the range within which a parasitic bipolar transistor in the lateral direction generated between the n-type gate, the p-type body (base), and the n-type source (emitter) and drain regions (collector) is not on, and therefore the body current is not so large as to cause a practical problem.
However, in the case of such a DTMOS structure, in order to suppress standby current, it is necessary to limit the voltage to be applied to the gate to up to about 0.6V, at which a parasitic bipolar transistor in the lateral direction is on. This is because the base current (the gate current or the body current that flows between the gate and the body in the DTMOS) of the parasitic bipolar transistor in the lateral direction is determined substantially by the built-in potential of the silicon, and therefore the gate current or the body current (base current) becomes significantly large when the gate bias voltage Vg (base voltage) is about 0.6V.
FIG. 7 is a graph showing simulation results of the gate bias voltage dependence of the drain current and the body current. The bold broken line in FIG. 7 shows the drain current Id of the conventional DTMOS, and the thin broken line in FIG. 7 shows the body current Ib of the conventional DTMOS. In FIG. 7, simulation is conducted with respect to the DTMOS that operates as a p-channel type MOS transistor, and therefore the gate bias voltage is negative values. However, in the case of an n-channel type DTMOS, the gate bias voltage is positive. These simulation results were obtained, assuming that the impurity concentration of the body is 1xc3x971018 atomsxc2x7cmxe2x88x923, the gate length is 0.5 xcexcm, and the thickness Tox of the gate insulator film is 10 nm. As seen from the curves of the broken lines in FIG. 7, in the conventional DTMOS shown in FIG. 1, the body current Ib is equal to or larger than the value (about 10xe2x88x929A) that causes a practical problem at 0.6V or more of the gate bias voltage. Therefore, in order to avoid this problem, the operating voltage range is limited to very narrow.
Furthermore, in the conventional DTMOS, the necessity of reducing the threshold voltage does not allow the impurity concentration of the body to be high. In fact, the above-described literature states that the concentration of the p-type impurity of the body is about 1.5 to 3xc3x971017 cmxe2x88x923. As a result, the resistance of the body becomes significantly high, so that the voltage drop at the body prevents efficient conduction of the electric potential of the gate to the channel region. As a result, a CR delay becomes detrimental to dynamic operations and inhibits high speed operations.
Moreover, since the concentration of the impurity of the body is low, the short channel effect that occurs when the gate length is made short becomes significant. This is because, when the gate length is short, the punch-through occurs readily between the source and the drain regions because of expansion of the depletion layer in the body. In other words, in the conventional DTMOS, it was practically difficult to improve the device performance or the integration degree by miniaturization of the size (miniaturization of the gate length) of the transistor.
It is an object of the present invention to provide a semiconductor device functioning as a DTMOS that has a low threshold voltage, can operate at a high speed, and has a wide operation range.
A semiconductor device of the present invention includes a substrate, a semiconductor layer provided in a part of the substrate, a gate insulator film provided on the semiconductor layer, a gate electrode provided on the gate insulator film, source and drain regions of a first conductivity type provided in regions on both sides of the gate electrode of the semiconductor layer, a channel region made of a first semiconductor provided in a region between the source and drain regions of the semiconductor layer, a body region of the second conductivity type made of a second semiconductor having a larger potential at a band edge where carriers travel than that of the first semiconductor, provided in a region below the channel region of the semiconductor layer; and a conductor member for electrically connecting the gate electrode and the body region.
Thus, the gate electrode and the body region are electrically connected, so that even if a voltage is applied to the gate electrode, the body region is maintained at substantially the same electric potential as that of the gate electrode. Therefore, no inversion layer is generated in a region other than the channel region of the semiconductor layer, and thus formation of a parasitic channel is suppressed. In addition, the channel region is constituted by the first semiconductor having a smaller potential at a band edge where carriers travel than that of the second semiconductor constituting the body region. Therefore, the gate bias necessary for inversion of the channel region, that is, the threshold voltage can be decreased. Consequently, the drain current is increased, and the difference between the drain current and the body (gate) current flowing in the channel increases. Thus, the operating voltage range can be extended. This is the same principle that is used for the hetero bipolar transistor in order to increase collector current while keeping the base current at the same level by using a material having a small band gap for the base layer in a bipolar transistor.
The present invention further includes a cap layer made of a semiconductor having a larger potential at a band edge where carriers travel than that of the first semiconductor, provided in a region between the channel region and the gate insulator film of the semiconductor layer. Thus, the gate insulator film can be constituted by an oxide film having good electric characteristics. On the other hand, since the gate electrode and the body region are electrically connected, even if the gate bias is increased, no parasitic channel is generated between the gate insulator film and the cap layer.
The operation speed of the semiconductor can be higher by constituting at least the uppermost portion of the substrate by an insulator, because the parasitic capacitance is reduced.
The increase of the threshold voltage can be suppressed, and impurity scattering can be suppressed by having the channel region contain impurities in a lower concentration than that of the body region by {fraction (1/10)} or less. Therefore, a reduction of the speed at which carriers travel can be suppressed.
A built-in potential is formed between the gate electrode and the channel region by constituting the gate electrode by polysilicon or polysilicon germanium containing impurities of the first conductivity. Thus, a band structure suitable for carrier confine can be obtained.
The first semiconductor constituting the channel region contains at least Si as a constituent element, and a portion of the semiconductor layer further includes a region for preventing impurities from diffusing to the channel that contains carbon in a concentration from 0.01% to 2%. With this embodiment, a semiconductor device that can operate at a high speed can be obtained, where scattering of impurities from the body region containing high concentration impurities to the channel region is suppressed, and impurity scattering hardly occurs in the channel region.
The first semiconductor is a semiconductor containing Si (silicon) and Ge (germanium) as constituent elements, and the second semiconductor is Si. With this embodiment, a channel region suitable for p-channel in which holes travel can be obtained by utilizing a band offset generated in the valence band edge of the first semiconductor pair.
The present invention further includes a cap layer made of Si, provided between the gate insulator film and the channel region. Thus, the region in contact with the band offset generated between the cap layer and the channel region of the channel region can be used as a channel. Moreover, the gate insulator film can be constituted by a silicon oxide film having good electric characteristics obtained by oxidizing the surface of the cap layer.
The source and drain regions may be p-type source and drain regions, the channel region may be a channel region for p-channel, and the body region may be an n-type body region. Alternatively, the source and drain regions may be n-type source and drain regions, the channel region may a channel region for n-channel, and the body region may be a p-type body region. With these components, a complementary transistor can be formed.
The first semiconductor is a semiconductor containing Si, Ge and C as constituent elements, and the second semiconductor is Si. Thus, a channel region that can be used both for n-channel and p-channel can be obtained, utilizing the band offsets at the conduction band edge and the valence band edge formed in the Si/SiGeC junction portion.
The first semiconductor may be Si under tensile strain, and the second semiconductor may be SiGe where lattice strain is relaxed.
A second semiconductor device of the present invention includes a substrate, a semiconductor layer provided in a part of the substrate, a gate insulator film provided on the semiconductor layer, a gate electrode provided on the gate insulator film, n-type source and drain regions provided in regions on both sides of the gate electrode of the semiconductor layer, a channel region for n-channel made of a first semiconductor containing Si and Ge as constituent elements and containing p-type impurities, provided in a region between the source and drain regions of the semiconductor layer, and a body region made of a second semiconductor containing Si as a constituent element and having a larger potential at a band edge where carriers travel than that of the first semiconductor, and containing p-type impurities, provided in a region below the channel region of the semiconductor layer.
The semiconductor device of the present invention further includes a cap layer containing Si as a constituent element and containing p-type impurities, provided in a region between the channel region and the gate insulator film of the semiconductor layer. Thus, a well suitable for confining electrons can be formed, utilizing the band offset at the conduction band edge formed between the cap layer and the channel region. Then, an n-channel type MIS transistor utilizing Si/SiGe junction can be obtained.
The semiconductor device of the present invention further includes a conductor member for electrically connecting the gate electrode and the body region. Thus, a semiconductor device that functions as a DTMOS can be obtained.
At least the uppermost portion of the substrate is constituted by an insulator. Thus, a transistor utilizing a so-called SOI substrate that has a small parasitic capacitance and can operate in a high speed can be obtained.
It is preferable that the gate electrode is constituted by polysilicon or polysilicon germanium containing impurities of the first conductivity.
The first semiconductor may be SiGeC, and the second semiconductor may be Si.